1. Field of the Invention
The present invention pertains to the art of digital accumulators, particularly for hardware architectures for high-speed digital accumulators used in digital signal processing.
2. Art Background
A key element in many signal processing systems is the digital accumulator (digital integrator). Examples include phase accumulators for Numerically Controlled Oscillators (NCOs), and integrators such as those used in Cascaded Integrator-Comb filters. The device is composed of a register and an adder in a feedback configuration. As the number of symbols (one or more bits or the equivalent of one or more bits in non-binary systems) increases, the maximum clock rate that may be realized generally decreases with the primary limitation being the carry propagation requirements of the adder. This can be a serious constraint on the achievable speed for very wide accumulators. The feedback nature of the structure suggests that a common technique to increase the speed of feed-forward structures, pipelining, may not be employed. Designers in the past would generally employ various carry speedup methods, but the amount of speedup achievable is limited without large increases in gate count.
What is needed is a method for speeding up digital accumulators.